820-01521MacBook Air (Retina, 13-inch, 2018)

The logic board of the MacBook Air (Retina, 13-inch, 2018), model A1932, 2018, 13-inch. 6 known faults with their symptoms below.

Model number: A1932
Year: 2018
Revisions: Rev A

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Identity and revisions

Brand: Apple
Device: MacBook Air
Model: A1932
Identifier: MacBookAir8,1
Board: 820-01521
Revisions: A

Power rails, in sequence

Net	Nominal	Role
PPDCIN_G3H	20 V	Charger input behind the CD3215 DC-in MOSFETs; matches the meter (5 V or 20 V)
PPBUS_G3H	12.62 V	Main bus from U7000 (ISL9240) or the battery; 12.60 to 12.65 V normal, 12.28 to 12.35 V while the T2 has not booted
PP3V3_G3H_RTC	3.3 V	3.3 V from U6960 for the CD3215s; missing means stuck at 5 V
PP3V3_UPC_XA_LDO	3.3 V	CD3215 U3100 LDO; over 1 kΩ to ground
PP3V3_UPC_XB_LDO	3.3 V	CD3215 U3200 LDO; powers the TBT ROM
PP5V_G3S	5 V	Calpe PMU G3S rail; under 4.9 V is abnormal
PP3V3_G3S	3.3 V	Calpe PMU G3S rail; under 3.215 V is abnormal
PP1V8_G3S	1.8 V	Calpe PMU G3S rail; under 1.70 V is abnormal
PP3V_G3H	3 V	3.0 V; under 2.915 V is abnormal
PP1V8_SLPS2R	1.8 V	U7800 output for the T2; kilohms to ground
PP1V1_SLPS2R	1.1 V	U7800 output for the T2; 50 to 100 Ω to ground is normal
PP0V9_SLPDDR	0.9 V	U7800 output; low resistance to ground is normal
PPVDDCPU_AWAKE	1.06 V	U7800 output for the T2 CPU
PP0V82_SLPDDR	0.82 V	U7800 output
PP3V3_S5	3.3 V	Intel S5 rail asserted by the T2
PP1V8_S5	1.8 V	Intel S5 rail

Checked on 2026-10-29 against 2 sources: verified. Revision A is a placeholder until Studio records the real revisions.

Known faults

5 V at 0.00 to 0.02 A: PPBUS_G3H short or creation (ISL9240, CD3215)
Seen in 25% of recorded fixes on this board.
Symptoms
5 V, 0.00 to 0.02 A on every port.
Parts involved
U7000
The fix, the readings that point to it and the guided tree are in the app. Free account
Corrupt T2 firmware (DFU or Recovery)
Seen in 20% of recorded fixes on this board.
Symptoms
12.28 to 12.35 V on PPBUS_G3H. 20 V at 0.03 to 0.06 A.
The fix, the readings that point to it and the guided tree are in the app. Free account
5 V cycling at 0.10 to 0.25 A: CD3215 to TBT ROM communication
Seen in 15% of recorded fixes on this board.
Symptoms
One port cycles. Corrosion near a CD3215.
Parts involved
U3200, C3208, U3100, C3108, U2890
The fix, the readings that point to it and the guided tree are in the app. Free account
Calpe PMU U7800 rails missing without a short
Seen in 15% of recorded fixes on this board.
Symptoms
Very low current at 5 V or 20 V. SLPS2R and AWAKE rails cycling. P5VG3S_EN missing.
Parts involved
U7800
The fix, the readings that point to it and the guided tree are in the app. Free account
20 V at 0.03 to 0.06 A: short on PP3V3_S5 or PP1V8_S5
Seen in 10% of recorded fixes on this board.
Symptoms
20 V, 0.03 to 0.06 A.
Parts involved
U4885
The fix, the readings that point to it and the guided tree are in the app. Free account

Compatible donors

Donor boards

820-01521 (CD3215C00 and ISL9240 from a donor; the 2018 and 2019 Airs share this board number)

Sister boards and shared circuits

820-01958: ISL9240 at U7000, U6960 RTC buck, Calpe PMU U7800, backlight driver U8400 with F8400 and R8442

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Identity and revisions

Brand: Apple
Device: MacBook Air
Model: A1932
Identifier: MacBookAir8,1
Board: 820-01521
Revisions: A

Power rails, in sequence

Net	Nominal	Role
PPDCIN_G3H	20 V	Charger input behind the CD3215 DC-in MOSFETs; matches the meter (5 V or 20 V)
PPBUS_G3H	12.62 V	Main bus from U7000 (ISL9240) or the battery; 12.60 to 12.65 V normal, 12.28 to 12.35 V while the T2 has not booted
PP3V3_G3H_RTC	3.3 V	3.3 V from U6960 for the CD3215s; missing means stuck at 5 V
PP3V3_UPC_XA_LDO	3.3 V	CD3215 U3100 LDO; over 1 kΩ to ground
PP3V3_UPC_XB_LDO	3.3 V	CD3215 U3200 LDO; powers the TBT ROM
PP5V_G3S	5 V	Calpe PMU G3S rail; under 4.9 V is abnormal
PP3V3_G3S	3.3 V	Calpe PMU G3S rail; under 3.215 V is abnormal
PP1V8_G3S	1.8 V	Calpe PMU G3S rail; under 1.70 V is abnormal
PP3V_G3H	3 V	3.0 V; under 2.915 V is abnormal
PP1V8_SLPS2R	1.8 V	U7800 output for the T2; kilohms to ground
PP1V1_SLPS2R	1.1 V	U7800 output for the T2; 50 to 100 Ω to ground is normal
PP0V9_SLPDDR	0.9 V	U7800 output; low resistance to ground is normal
PPVDDCPU_AWAKE	1.06 V	U7800 output for the T2 CPU
PP0V82_SLPDDR	0.82 V	U7800 output
PP3V3_S5	3.3 V	Intel S5 rail asserted by the T2
PP1V8_S5	1.8 V	Intel S5 rail

Checked on 2026-10-29 against 2 sources: verified. Revision A is a placeholder until Studio records the real revisions.

Known faults